Disk drives are widely accepted as a cost effective data storage system for a computer, music player or other data processing devices. As shown in FIG. 1, a disk drive system 10 comprises a magnetic recording medium, in the form of a disk or platter 12 having a hub 13 and a magnetic read/write transducer 14, commonly referred to as a read/write head. The read/write head 14 is attached to or formed integrally with a suspension arm 15 suspended over the disk 12 and affixed to a rotary actuator arm 16. A structural arm 18, supported by a platform 20, is pivotably connected to the actuator arm 16 at a pivot joint 22. A voice coil motor 24 drives the actuator arm 16 to position the head 14 over a selected position on the disk 12.
As a spindle motor (not shown) rotates the disk 12, the moving air generated by the rotating disk in conjunction with the physical features of the suspension arm 15 lifts the read/write head 14 away from the platter 12, allowing the head 14 to glide or fly on a cushion of air slightly above an upper surface of the disk 12. The flying height of the read/write head 14 over the disk surface is typically less than a micron.
An arm electronics module 30 may include circuits that switch the head function between read and write operations, a write driver for supplying write current to the head 14 during write operations and an amplifier for amplifying the read signal. The arm electronics module 30 is connected to the head 14 by flexible conductive leads 32
The configuration and components of the electronics module 30 vary according to the disk drive design as will be understood by persons familiar with such technology. Although the module 30 may be mounted anywhere in the disk drive 10, a location proximate the head 14 minimizes signal losses and induced noise in the head signals during a read operation. A preferred mounting location for the module 30 comprises a side surface of the structural arm 18 as shown in FIG. 1.
The disk 12, shown in a partial cross-sectional schematic view in FIG. 2 comprises a substrate 50 and a thin film 52, disposed thereover. The magnetic transducer or head 14 comprises a write head 14A for writing data bits to the disk 12 by altering magnetic domains of ferromagnetic material in the film 52, thereby creating magnetic transitions in the magnetic domains. A read head 14B reads the magnetic transitions to determine the stored data bit.
Data bits and timing information to be written to the disk 12 are supplied by a data processing device 60 (e.g. a computer or music player) in the form of bipolar data pulses in PECL (positive emitter-coupled logic) form. Typically, the PECL bipolar signals representing a logic one and a logic zero differ by about 200 mV or by about 450 mV. The data and timing pulses are supplied to a data write circuit 62 where the data bits are formatted and error detection/correction information appended thereto.
To write data bits, the voice coil motor 18 moves the suspension arm 16 to a desired radial position above the surface of the disk 12 while the spindle motor rotates the disk 12 to move a circumferential region to be written under the write head 14A. A write driver 66A of a preamplifier 66 (in one embodiment the preamplifier 66 is disposed within the electronics module 30) supplies a write current (in certain applications between about 10 mA and 70 mA) to the write head 14A responsive to the signal from the data write circuit 62. The write driver 66A scales up the relatively low voltage levels representing the data bits to a voltage range between about +/−6V and +/−10V. In one embodiment the write driver 66A converts the PECL signals to logic signals having a larger differential voltage, such as about 3.3V. The write driver 66A also shapes the write current signal waveform to optimize the data writing process.
Write current supplied by the write driver 66A to the write head 14A (magnetically coupled to a magnetically permeable core not shown) creates a magnetic field that extends from the core across an air gap between the write head 14A and the disk 12. The magnetic field alters a region of ferromagnetic domains in the thin film 52 to store the data bits as magnetic transitions.
The direction of the magnetic field generated by the write head 14A, and thus the direction of the altered ferromagnetic domains, is responsive to the direction of current flow through the write head 14A. Current supplied in a first direction through the write head 14A aligns the domains in a first direction (representing a date 0 for example) and current supplied in a second direction (representing a data 1 for example) aligns the domains in a second direction.
In the read mode, transitions between adjacent domains are detected to determine the stored data bit. The read head 14B (comprising either a magneto-resistive (MR) sensor or an inductive sensor) senses the magnetic transitions in the thin film 52 to detect the stored data bits. A differential output signal produced by the MR sensor responsive to the magnetic transitions has a higher magnitude and a higher signal-to-noise ratio than an output signal produced by the inductive sensor. The MR sensor is thus preferred, especially when a higher areal data storage density is desired. State-of-the-art MR read heads include giant magnetoresistive (GMR) heads and tunneling magnetoresistive (TMR) heads.
The suspension arm 16 moves the head 14 while the disk 12 rotates to position the read head 14B above a magnetized region to be read. A DC (direct current) bias voltage of between about 0.025V and about 0.3V is supplied to the read head 14B by a read circuit 66B of the preamplifier 66. Magnetic domains in the thin film 52 passing under the read head 14B alter a resistance of the magneto-resistive material, imposing an AC (alternating current) component on the DC bias voltage. The AC component representing the read data bits has a relatively small magnitude (e.g., several millivolts) with respect to the DC bias voltage.
The differential read output signal, having an amplitude in a range of several millivolts, is input to a signal processing stage 102 followed by an output or converter stage 104. Typically, both the signal processing stage 102 and the output stage 104 are elements of the preamplifier 66. The signal processing stage 102 amplifies the signal to increase the signal's signal-to-noise ratio. The output stage 104 scales up the head signal voltage to a peak voltage value in a range of several hundred millivolts, supplying the scaled-up signal to channel circuits of a channel chip 106 through an interconnect 108. The channel chip 106 detects the read data bits from the voltage pulses, while applying error detection and correction processes to the read data bits. The read data bits are returned to the processing device 60 via a user interface 110 (e.g., SATA, SCSI, SAS, PCMCIA interfaces).
In other data storage systems the head 14 operates with different types of storage media (not shown in the Figures) comprising, for example, a rigid magnetic disk, a flexible magnetic disk, magnetic tape and a magneto-optical disk.
To increase storage capacity, a disk drive may comprise a plurality of stacked parallel disks 12. A read/write head is associated with each disk to write data to and read data from a top and bottom surfaces of each disk.
Integrated circuits such as the electronics module 30 described above, typically comprise a silicon semiconductor substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. Interconnect structures are formed in parallel-like layers overlying the semiconductor substrate to provide electrical connection between devices to form electrical circuits. A conventional interconnect system comprises a plurality of substantially vertical conductive vias or plugs and substantially horizontal conductive interconnect runners or traces, with a dielectric layer disposed between two vertically adjacent interconnect layers. The uppermost interconnect layer comprises a plurality of bond pads for receiving conductive bond wires or solder balls to interconnect the devices of the integrated circuit to off-chip external contacts, such as pins or leads of a package structure.
The integrated circuits are fabricated by forming regions of different materials, such as doped regions, dielectric regions and conductive regions, in a semiconductor wafer and on an upper surface thereof. Hundreds of such integrated circuits or die are formed on a single wafer by performing a plurality of sequential fabrication process steps (e.g., implanting and diffusing dopants, depositing materials on the upper surface of the wafer, patterning conductive regions) to form multiple die in the wafer, each die comprising active devices, passive devices (e.g., capacitors and resistors) and the interconnect structures. The manufacturing process steps are carefully developed to maximize the number of integrated circuits that satisfy desired operational specifications.
After completion of the fabrication steps, each die undergoes electrical testing (referred to as wafer probe testing) so that only those die that satisfy applicable performance specifications are accepted. After the wafer is singulated, the accepted die are packaged to protect the integrated circuit from contamination and damage. Package leads provide electrical connection of the integrated circuit to other electronic components, such as electronic components mounted on a printed circuit board with the packaged integrated circuit.
It is necessary for the preamplifier 66 of the electronics module 30 to provide an accurate read head bias (i.e., a DC voltage bias or a DC current bias) to avoid head degradation and improve data reading accuracy. Each preamplifier is evaluated during the wafer probe test to stage to determine whether the bias is within specifications. During the test, the preamplifier is powered through test probes that supply the necessary externally generated power supply voltages to certain conductive pads of the preamplifier integrated circuit. The bias voltage generated on-chip is then measured by test probes in contact with other conductive pads.
It is known that contact resistance between a wafer probe tip and the associated contact region of a bond pad can cause bias measurement errors. Further, contact resistance can increase as testing progresses among die on a wafer as the probe tips collect dirt from the wafer surface. Increased probe tip resistance can cause substantial errors in the measured value of the bias voltage, possibly resulting in misidentification and rejection of otherwise good preamplifiers—or passing unacceptable preamplifiers as acceptable.
A similar bias test is performed for preamplifiers that supply a bias current. The bias current is determined by causing the bias current to flow through a know resistance connected to the wafer test probes and measuring the voltage across the resistance.
A prior art head bias wafer probe test circuit 199 depicted in FIG. 3 is one such test probe circuit sensitive to the effects of wafer probe contact resistance when the bias voltage (or current) is measured. A preamplifier on-chip circuit, represented by a voltage source 200, generates and supplies a bias voltage to input/output pads HRP and HRN during the wafer probe test. When the preamplifier is operational in the disk drive data storage system 10, the input/output pads HRP and HRN are connected to the read head 14B. In the circuit 199, a load resistor RMR, having a resistance equivalent to a nominal head resistance, is connected across the input/output pads HRP and HRN and a voltage measured across these pads indicates the bias voltage. The wafer probe resistances are modeled in FIG. 3 by resistors RPAR1 and RPAR2. A voltage measured by the voltmeter 202 is:
                              V          MEASURED                =                              V            BIAS                    ⁡                      (                                          R                MR                                                              R                  MR                                +                                  R                  PAR1                                +                                  R                  PAR2                                                      )                                              (        1        )            
When probing many die across the wafer the probe tips become dirty and the contact resistances RPAR1 and RPAR2 increase. As can be seen from equation (1), the increased resistance lower the measured voltage relative to the bias voltage. When the disparity between the measured voltage and the bias voltage is so great as to cause the measured voltage to fall below a minimum acceptable bias voltage value, the preamplifier may be rejected as unacceptable. Thus the probe tip contact resistance can adversely influence yield determinations by identifying as faulty devices that generate a correct bias voltage.
The error in the measured voltage is the difference between the actual bias voltage VBIAS and the measured voltage VMEASURED:
      Error    ⁢                  [    %    ]    =            (                                    R            MR                                              R              MR                        +                          R              PAR1                        +                          R              PAR2                                      -        1            )        *    100    ⁢    %  
For a nominal value of RMR=40Ω (for a GMR read head) and expected values of 0.50Ω for each of RPAR1 and RPAR2, the error is:
      Error    ⁢                  [    %    ]    =                    (                                            R              MR                                                      R                MR                            +                              R                PAR1                            +                              R                PAR2                                              -          1                )            *      100      ⁢      %        =                            (                                    40                              40                +                0.50                +                0.50                                      -            1                    )                *        100        ⁢        %            =              2.4        ⁢        %            It is known that as the probes become dirty during testing the contact resistance can typically increase to a few ohms, thereby increasing the percentage measurement error.
Current methods for detecting an unacceptably high probe contact resistance include monitoring the measured bias voltage to identify declining voltage values and monitoring the results of any tests that are sensitive to probe contact resistance, such as the bias measurement test of FIG. 3. After an unusually large number of integrated circuits are identified as faulty the test sequence may be paused while the probe tips are cleaned (to reduce the contact resistance) and devices previously identified as faulty are retested. The retesting process wastes time and adds cost to the wafer probe tests. Furthermore, some integrated circuits that passed the wafer probe test prior to probe cleaning may have been faulty.
The combination of various fabrication and operational anomalies can cause performance parameters of an integrated circuit (such as the bias voltage or current) to vary. These variations may cause the parameter to exceed an acceptable range above or below a nominal value. These variations must be controlled to ensure the performance parameters are within the acceptable range and the testing process must properly identify the devices that are outside the acceptable range.
By way of example, the total allowable variation in the bias voltage measurement of a preamplifier may be limited to 7 percent. Factors contributing to this range include fabrication process limitations and operational anomalies that directly affect the bias voltage or current generated on the integrated circuit, and the aforediscussed wafer test anomalies that affect the measured value. The cumulative fabrication and operational anomalies may introduce considerable measurement variability, leaving little head room to accommodate anomalies of the testing process.
It is not uncommon to encounter a variation of 1–1.5 percent in a bias reference circuit (e.g., a band-gap voltage reference) that supplies the reference voltage (or current) to the circuit elements that generate the head bias voltage (or current). Operating temperature, semiconductor process variations and mismatches between integrated circuit devices may add another 2–4 percent. Adding variations in wafer probe contact resistance causes the cumulative variation to approach and perhaps exceed the 7 percent limit, especially as the contact resistance increases. Most test processes use an error margin or guard band of about 1 percent lowering the acceptable margin from 7 percent to 6 percent, further increasing the probability that the cumulative error specification will not be satisfied.
If the cumulative effect of the several factors contributing to test circuit error exceed a specified limit, e.g., 7 percent, there will be an increase in the number of die that fail the probe test because of error associated with the test circuitry and the measurement process. The number of failed integrated circuits therefore increases. While it is important to reduce the contribution of each anomaly to the cumulative measurement error, such reductions may be costly. For example, reducing the effects of fabrication anomalies may require the development of new process steps or the purchase of new process equipment that permits tighter control over the fabrication process and reduces variations in measurable parameters, such as voltages. Clearly there is a need to reduce the effects of probe contact resistance to minimize error associated with bias voltage measurement.